The present invention relates to a semiconductor memory device and a method for manufacturing the same.
In a conventional nonvolatile semiconductor memory device, a space between word lines is filled with an oxide film or a nitride film. However, along with miniaturization of elements, the spacing between word lines becomes shorter, and parasitic capacitance generated between floating gate electrodes of adjacent word lines or between a floating gate and a diffusion layer reduces writing speed.
In order to solve the above-described problem, there has been proposed the process of reducing parasitic capacitance by depositing an oxide film with a poor filling ability on and between word lines and providing an air gap (cavity) between adjacent floating gate electrodes.
The spacing between a selecting gate transistor and a word line adjacent thereto (hereinafter referred to as an end WL) needs to be larger than that between word lines for the following two purposes. The first purpose is to leave an offset space between a diffusion layer region formed at the surface of a part of a substrate between the selecting gate and the end WL and an end (side surface) of the selecting gate and prevent an abnormal cutoff of the selecting gate due to a GIDL (gate inducted drain leakage) flowing between a gate and a drain which is generated upon extension of a depletion layer from the diffusion layer region when the gate voltage of the selecting gate becomes negative.
The second purpose is to secure an alignment tolerance for a resist having an opening corresponding to a memory cell array portion and covering a selecting gate region at the time of performing double patterning in order to form a memory cell array. Examples of double patterning include a method for realizing double-fineness circuit pattern drawing by preparing two masks bearing staggered circuit patterns, exposing one wafer twice using the two masks, and overlaying one circuit on another in a staggered configuration and a method for realizing a micropattern at a lower layer using side wall films formed at side walls of a formed dummy pattern.
If a conventional air gap forming method as described above is applied to a semiconductor memory device in which the spacing between each selecting gate transistor and the corresponding end WL is long, it is impossible to form an air gap between the selecting gate transistor and the end WL.
For this reason, parasitic capacitance (parasitic fringe capacitance) generated between each end WL and a corresponding diffusion layer cannot be reduced, and the writing speed of the end WL cannot be improved.